PIC16F785-I/SS【PDF 12/206 页】IC PIC MCU FLASH 2KX14 20SSOP

收藏本站

您好，
买卖IC网欢迎您。
请登录
免费注册

买卖IC网

Sheet目录3887

8页 9页 10页 11页 [12页]13页 14页 15页 16页

109

8272E–AVR–04/2013

ATmega164A/PA/324A/PA/644A/PA/1284/P

15.9.6

TIMSK0 – Timer/Counter Interrupt Mask Register

Bits 7:3 – Reserved

These bits are reserved and will always read as zero.

Bit 2 – OCIE0B: Timer/Counter Output Compare Match B Interrupt Enable

When the OCIE0B bit is written to one, and the I-bit in the Status Register is set, the

Timer/Counter Compare Match B interrupt is enabled. The corresponding interrupt is executed if

a Compare Match in Timer/Counter occurs, that is, when the OCF0B bit is set in the

Timer/Counter Interrupt Flag Register – TIFR0.

Bit 1 – OCIE0A: Timer/Counter0 Output Compare Match A Interrupt Enable

When the OCIE0A bit is written to one, and the I-bit in the Status Register is set, the

Timer/Counter0 Compare Match A interrupt is enabled. The corresponding interrupt is executed

if a Compare Match in Timer/Counter0 occurs, that is, when the OCF0A bit is set in the

Timer/Counter 0 Interrupt Flag Register – TIFR0.

Bit 0 – TOIE0: Timer/Counter0 Overflow Interrupt Enable

When the TOIE0 bit is written to one, and the I-bit in the Status Register is set, the

Timer/Counter0 Overflow interrupt is enabled. The corresponding interrupt is executed if an

overflow in Timer/Counter0 occurs, that is, when the TOV0 bit is set in the Timer/Counter 0 Inter-

rupt Flag Register – TIFR0.

15.9.7

TIFR0 – Timer/Counter 0 Interrupt Flag Register

Bits 7:3 – Reserved

These bits are reserved and will always read as zero.

Bit 2 – OCF0B: Timer/Counter 0 Output Compare B Match Flag

The OCF0B bit is set when a Compare Match occurs between the Timer/Counter and the data in

OCR0B – Output Compare Register0 B. OCF0B is cleared by hardware when executing the cor-

responding interrupt handling vector. Alternatively, OCF0B is cleared by writing a logic one to

the flag. When the I-bit in SREG, OCIE0B (Timer/Counter Compare B Match Interrupt Enable),

and OCF0B are set, the Timer/Counter Compare Match Interrupt is executed.

Bit 1 – OCF0A: Timer/Counter 0 Output Compare A Match Flag

The OCF0A bit is set when a Compare Match occurs between the Timer/Counter0 and the data

in OCR0A – Output Compare Register0. OCF0A is cleared by hardware when executing the cor-

responding interrupt handling vector. Alternatively, OCF0A is cleared by writing a logic one to

the flag. When the I-bit in SREG, OCIE0A (Timer/Counter0 Compare Match Interrupt Enable),

and OCF0A are set, the Timer/Counter0 Compare Match Interrupt is executed.

Bit

(0x6E)

–

OCIE0B

OCIE0A

TOIE0

TIMSK0

Read/Write

RRRR

R/W

Initial Value

Bit

543210

0x15 (0x35)

–

–OCF0B

OCF0A

TOV0

TIFR0

Read/Write

RRRRR

R/W

Initial Value

000000

发布紧急采购，3分钟左右您将得到回复。

采购需求

(若只采购一条型号，填写一行即可)

*型号	*数量	厂商	批号	封装

添加更多采购

采购需求

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

我的联系方式